Aborts

There is an abort line entering the ARM processor which can be pulled high by an external memory manager when the ARM attempts an illegal access to memory. The ARM has two abort traps, depending on what it was attempting to do when it received the abort. If it was attempting to fetch data from an illegal address, it enters abt mode and jumps to 0x10, and if it attempts to execute an instruction which is marked as having been from an illegal addressthen it enters abt mode and jumps to 0x0C. In either case, it preserves the return address in R14_abt.

When the ARM attempts to execute an instruction which it does not understand it enters und mode, stores the address of the instruction following the undefined one in R14_und and jumps to address 0x04. This is normally used to implement a software floating point emulator in machines with no floating point hardware. Unfortunately, there is no freely available floating point emulator for the ARM, and this is someting that would need to be implemented.

Versions of the ARM before the ARM6 did not have abt or und modes. In the ARM2 and ARM3, when illegal memory accesses or undefined instructions occur, the ARM switches into svc mode instead. This makes it very difficult to implement a virtual memory system since if the processor is in svc mode and it accesses memory which is not currently paged in then R14_svc, which would normally contain the return address from the system call, will be overwritten with the address of the aborting instruction. To get around this, it is necessary to preserve the return address into a different register before attempting to access any memory, possibly including the svc stack. Acorn's RISCiX (a derivative of 4.3BSD Unix) works in this manner. Acorn's RISC OS does not bother, and simply does not implement virtual memory. Under RISC OS, it is also not normally permitted to issue floating point instructions while in svc mode since this will also overwrite R14_svc.